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1 lt1619 low voltage current mode pwm controller , ltc and lt are registered trademarks of linear technology corporation. the lt ? 1619 is a fixed frequency pwm controller for implementing current mode dc/dc converters with mini- mum external parts. the lt1619 operates with input voltage ranging from 1.9v to 18v and is suitable for a variety of battery-powered and distributed dc/dc con- verters. the internal rail-to-rail n-channel mosfet driver operates either from the input in the nonbootstrapped mode or from the output in bootstrapped operation. the driver is designed to drive a low side power transistor in boost, sepic, flyback and other topologies. converter efficiency is improved at heavy loads with a 53mv current sense voltage and at light load with burst mode operation. the operating frequency is internally set at 300khz. the oscillator can also be synchronized exter- nally up to 500khz. no load quiescent current is 140 m a and shutdown current is 15 m a. the lt1619 is available in 8-lead msop and so packages. n wide v in range: 1.9v to 18v n 300khz fixed frequency current mode control n 1a rail-to-rail n-channel mosfet driver n low 53mv current limit threshold voltage improves efficiency n implements boost, sepic and flyback converters requiring low side power transistors n internal current sense amplifier with leading edge blanking n up to 500khz external synchronization n burst mode tm operation for high efficiency at light load n 140 m a quiescent current n 15 m a shutdown current n 8-lead msop and so packages n 3.3v to 5v dc/dc converters n distributed power supplies n isolated power supplies figure 1. high efficiency 3.3v to 5v dc/dc converter burst mode is a trademark of linear technology corporation. load current (ma) 75 efficiency (%) 80 85 90 95 1 100 1000 1619 f01a 70 10 efficiency features descriptio u applicatio s u typical applicatio u + 0.1 f 0.1 f 15nf 220pf v in 3.3v l1 5.6 h 5a d1 m1 si9804 v out 5v 2.2a r sense 0.01 1619 f01 75k r1 37.4k r2 12.4k c1 22 f c1: panasonic eefcdok220r c out : kemet t495x227k010as ( 2) d1: mbrd835l l1: coilcraft do5022p-562 + c out 440 f s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense lt1619
2 lt1619 input voltage (v in ) ................................... C 0.3v to 20v gate drive supply voltage (drv) ............. C 0.3v to 20v shutdown/synch voltage (s/s) ................ C 0.3v to 20v feedback voltage (fb) .............................................. v in compensation voltage (v c ) ...................................... 3v gate drive output current (gate) ........................ 1.5a current sense voltage (sense) ................. C 0.5v to v in operating temperature range (note 2) .. C 40 c to 85 c junction temperature (note 3) ............................. 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c consult factory for military grade parts. t jmax = 125 c, q ja = 200 c/ w t jmax = 125 c, q ja = 120 c/ w (note 1) order part number ms8 part marking lt1619ems8 lthc 1 2 3 4 s/s fb v c gnd 8 7 6 5 v in drv gate sense top view ms8 package 8-lead plastic msop order part number s8 part marking lt1619es8 1619 1 2 3 4 8 7 6 5 top view v in drv gate sense s/s fb v c gnd s8 package 8-lead plastic so parameter conditions min typ max units reference voltage measured at the fb pin l 1.22 1.24 1.26 v reference line regulation 1.9v v in 18v 0.004 0.05 %/v fb input bias current v fb = v ref 10 25 na error amplifier transconductance 80 170 260 mw C1 error amplifier output source current v fb = 1v, v comp = 1v 4 8.7 14 m a error amplifier output sink current v fb = 1.5v, v comp = 1v 4 8.7 14 m a error amplifier clamp voltage v fb = 1v 1.6 2.2 v undervoltage lockout threshold 1.65 1.85 v input voltage range l 1.9 18 v switching frequency 1.9v v in 18v l 220 300 360 khz synchronization frequency range 370 500 khz maximum duty cycle l 88 92 % current limit threshold l 40 53 66 mv burst mode operation current limit 10 mv the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = v drv = 2.5v, v s/s = v in , comp open, v sense = 0v unless otherwise noted. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics
3 lt1619 parameter conditions min typ max units current sense input current v sense = 0v l C 90 C 120 C 150 m a current limit delay 150 ns driver output rise time c l = 3300pf 30 ns driver output fall time c l = 3300pf 35 ns driver output high level i out = C 20ma v drv C 0.6 v drv C 0.35 v i out = C 200ma v drv C 1.6 v drv C 1.2 v driver output low level i out = 20ma 100 200 mv i out = 200ma 0.5 0.7 v shutdown driver output level v s/s = 0v, i out = 20ma 100 200 mv idle mode driver output level v s/s = v in , v fb = 1.5v, i out = 20ma 100 200 mv s/s pin current v s/s = v in 4 m a v s/s = 0v C 2 m a operating supply current v fb = 1v 9 ma quiescent supply current v s/s = v in , v fb = 1.5v l 140 220 m a shutdown supply current v s/s = 0v 15 19 m a v s/s = 0v, v in = 18v, t a = 85 c40 m a shutdown threshold 0.45 1.2 v shutdown delay 12 17 33 m s the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = v drv = 2.5v, v s/s = v in , comp open, v sense = 0v unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: the lt1619e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a , the power dissipation p d and the thermal resistance q ja of the package according to the formula: t j = t a + p d ? q ja electrical characteristics typical perfor a ce characteristics uw bandgap voltage vs temperature i s/s vs v s/s s/s pin current vs temperature temperature ( c) ?0 bandgap voltage (v) 1.241 1.243 80 100 1619 g01 ?0 0 20 40 60 120 1.245 1.235 1.227 1.225 1.233 1.231 1.229 1.237 1.239 v in = 2.5v v s/s (v) 0 i s/s ( a) 5 4 3 2 1 0 ? ? ? 4.0 1619 g02 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 t a = 40 c t a = 25 c t a = 85 c temperature ( c) ?0 s/s pin current ( a) 1 3 120 1619 g03 ? ? 0 40 80 ?0 20 60 100 5 0 2 ? 4 v s/s = 0v v s/s = 2.5v
4 lt1619 typical perfor a ce characteristics uw shutdown supply current vs input voltage idle mode supply current vs temperature frequency deviation from nominal vs temperature input voltage (v) 0 supply current ( a) 45 40 35 30 25 20 15 10 5 16 1619 g04 4 8 12 20 14 2 6 10 18 t a = 40 c t a = 85 c t a = 25 c temperature ( c) ?0 140 idle mode supply current ( a) 150 160 170 180 040 80 120 1619 g05 190 200 ?0 20 60 100 v in = 2.5v temperature ( c) ?0 deviation from nominal frequency (%) 8 20 1619 g06 2 ? ?0 0 40 ? ? ? ?0 10 6 4 0 60 80 100 v in = 2.5v nominal frequency = 300khz maximum duty ratio vs temperature deviation from nominal frequency vs input voltage current limit threshold vs temperature temperature ( c) 40 ?0 90 duty ratio (%) 92 95 0 40 60 1619 g07 91 94 93 20 80 100 v in = 2.5v input voltage (v) 0 frequency deviation (%) 2 4 6 16 1619 g08 0 ? ? 4 8 10 20 8 12 2 6 18 14 t a = 25 c nominal frequency = 300khz temperature ( c) ?0 current limit threshold (mv) 57 20 1619 g09 54 52 ?0 0 40 51 50 58 56 55 53 60 80 100 v in = 2.5v burst mode operation current limit threshold vs temperature sense pin input bias current vs temperature sense pin input bias current vs sense voltage temperature ( c) ?0 8 10 14 20 60 1619 g10 6 4 ?0 0 40 80 100 2 0 12 current limit threshold (mv) v in = 2.5v duty cycle = 0 temperature ( c) ?0 sense pin current ( a) ?15 ?17 ?19 ?21 ?23 ?25 ?27 ?29 ?31 ?33 ?35 0 40 60 1619 g11 ?0 20 80 100 v sense = 0v v sense (mv) ?0 sense pin current ( a) 60 1619 g12 010 20 30 40 50 ?0 ?5 100 105 110 115 120 125 130 t a = 25 c
5 lt1619 + + q r i lim 1619 f02 current limit comparator s s ++ + driver 280ns current sense amp gate drv v in 6 gnd 4 sense r sense load 5 7 leading edge blanking c1 sync ramp comp 300khz oscillator shutdown delay ref/bias s/s 1 fb 1.24v 1.8v v c v in clk idle uvlo + v b + a1 + a2 error amplifier 2 3 8 g m figure 2. lt1619 block diagram s/s (pin 1): shutdown and synchronization. shutdown is active low with a typical threshold voltage of 0.9v. for normal operation, the s/s pin is tied to v in . to externally synchronize the controller, drive the s/s pin with pulses. fb (pin 2): the inverting input of the error amplifier. connect the resistor divider tap here. set v out according to v out = 1.24(1 + r1/r2). see figure 1. v c (pin 3): compensation pin for the error amplifier. v c is the output of the transconductance amplifier. overall loop is compensated with an rc network from this pin to the ground. gnd (pin 4): ground. connect to local ground plane. sense (pin 5): the input of the current sense amplifier. the sense pin is connected to the source of the n-channel mosfet and to a sense resistor to the ground. the current limit threshold is internally set at 53mv, giving a maximum switch current of 53mv/r sense . gate (pin 6): the output of the mosfet driver. drv (pin 7): the pull-up supply of the mosfet driver. tie this pin to v in (pin 8) for nonbootstrapped operation or to the converter output for bootstrapped operation. v in (pin 8): supply or battery input. must be closely bypassed to the ground plane. uu u pi fu ctio s block diagra w
6 lt1619 the lt1619 is a fixed frequency current mode switching regulator pwm controller that can be used in boost, sepic or flyback modes. the device operates from an input supply range of 1.9v to 18v, and has a separate supply pin (drv) for the gate driver. the drv pin can be bootstrapped to v out for additional gate enhancement in low voltage applications like 3.3v to 5v boost converters, or con- nected to the input supply for higher voltage inputs. to best understand operation of the lt1619, please refer to figure 2, the block diagram. the gate drive circuit turns on the external mosfet at the trailing edge of oscillator output signal clk. mosfet current is sensed with an external resistor (r sense of figure 1). a leading edge blanking circuit disables the current sense amplifier for 280ns immediately following switch turn-on, preventing gate charging current from prematurely tripping the pwm comparator. a slope compensating ramp, derived from the oscillator, is added to the current sense output. the driver turns off the mosfet when this sum exceeds the error amplifier output v c . the switch current is limited with a separate comparator. the compensating ramp is a progressive nonlinear function of the operating duty ratio whereas the current limit does not vary with the duty ratio. error amplifier output v c determines the peak switch cur- rent required to regulate the output voltage. v c can be considered a measure of output current. at heavy loads, v c is in its upper range. average and peak inductor cur- rents are high. in this range, the inductor tends to run in continuous conduction mode (ccm), where current is al- ways flowing in the inductor. as load current decreases, average and peak inductor current decreases. when the average inductor current falls below 1/2 of the peak-to-peak inductor current ripple, the converter enters discontinu- ous conduction mode (dcm), where current in the induc- tor reaches zero sometime during the discharge phase. further reduction in output current moves v c towards its lower operating range, decreasing inductor current. hys- teretic comparator a1 determines if v c is too low for the lt1619 to operate efficiently. as v c falls below the trip voltage vb, a1s output goes high, turning off all blocks except the error amplifier, a1 and a2. the lt1619 enters the idle state and switching stops. the device draws just 140 m a from the input in the idle state. output load current discharges the output capacitor, causing the output volt- age to decrease. as v out decreases, v c increases. as v c increases above v b , switching action begins, delivering power to the output. the switch current sense threshold is about 10mv in this v c region. if the output load remains light, the output voltage will rise and v c will fall, causing the converter to idle again. this is known as burst mode operation. the burst frequency depends on input voltage, output voltage, inductance and output capacitance. out- put voltage ripple during burst mode operation is usually higher than when the converter is switching continuously. burst mode operation increases light load efficiency be- cause it delivers more energy per clock cycle than possible with discontinuous mode operation and extremely low peak switch current, allowing fewer switching cycles to maintain a given output. ic supply current therefore be- comes a small fraction of the total input current. setting output voltage the output voltage of the lt1619 is set with resistive divider r1 and r2 connected from the output to ground as detailed in figure 3. the divider tap is tied to the device fb pin. current through r2 should be significantly higher than the fb pin bias current of 25na. with r2 = 10k, the input bias current of the error amplifier is 0.02% of the current in r2. figure 3. feedback resistive divider synchronization and shutdown the s/s pin (pin 1) can be used to synchronize the oscillator to an external source. the s/s pin is tied to the input (v in > 1.9v) for normal operation. the oscillator in the lt1619 can be externally synchronized by driving the s/s pin with a pulse train with an amplitude of at least 1v. the maximum allowable rise time is a function of the pulse amplitude, as shown in table 1. rise times equal to operatio u v o r1 r1 r2 v o = 1.24v 1 + ?1 r2 1619 f03 () v o 1.24 r1 = r2 () lt1619 fb
7 lt1619 operatio u inductor the value of the inductor is usually selected so that the peak-to-peak ripple current is less than 30% of the maxi- mum inductor current. the inductor should be able to handle the maximum inductor current at full load without saturation. powder iron cores are not suitable for high frequency switch mode power supply applications be- cause of their high core losses. ferrite cores have very low core losses and are the material of choice for high fre- quency dc/dc converters. power mosfet driver the lt1619 is capable of driving a low side n-channel power mosfet with up to 60nc of total gate charge (q g ). an external driver is recommended for mosfets with greater than 80nc of total gate charge. the peak gate drive current varies from 0.5a with v drv = 2.5v to 1.2a with v drv = 10v. the mosfet driver is capable of charging the gate of the power mosfet to within 350mv of the upper gate drive supply rail (drv). it can also pull the gate of the mosfet to within 100mv of ground during turnoff. the upper supply rail of the gate drive is brought out as a device pin (drv) for design flexibility. in a boost converter design, the drv pin can be tied to the converter output if the minimum input voltage is insufficient to fully enhance the power mosfet. during start-up, the mosfet is driven with a gate voltage starting from v in C v d (v d is the forward voltage of the rectifying diode). as the output voltage rises, the gate drive also increases until steady state is reached. if the steady-state converter output voltage exceeds the maximum allowable gate source voltage and the input voltage is sufficient to enhance the mosfet, the drv pin is tied to the input supply. for a sepic converter, the drv pin can be tied to the input or diode ored from the input and the output (figure 4). figure 4. sepic converter with diode ored gate drive supply or less than the number specified in table 1 are accept- able. the maximum duty cycle is essentially unaffected by synchronization. the device will go into shutdown mode if the s/s pin voltage stays below the shutdown threshold of 0.45v for more than 33 m s. this shutdown delay is reset whenever the s/s pin voltage rises above the shutdown threshold. applying a logic low signal at the s/s pin causes the gate drive output to go low. although all circuits in the lt1619 are disabled, the pull-down circuit in the mosfet buffer is still biased on. it is capable of shunting any leakage or transient current at the gate pin to ground, eliminating the need for an external bleed resistor. the lt1619 con- sumes 15 m a in shutdown. the lt1619 is guaranteed to start with a minimum v in of 1.85v. comparator a2 senses the input voltage and gen- erates an undervoltage lockout (uvlo) signal if v in falls below this minimum. while in undervoltage lockout, v c is pulled low and the lt1619 stops switching. the supply current drawn by the device falls to 140 m a. table 1. maximum allowable rise time of synchronization pulse. rise time can be slower if clock amplitude is higher synchronization maximum allowable amplitude (v) rise time (ns) 1.2 120 1.5 220 2.0 350 2.5 470 3.0 530 drv v in v out r s 1619 f03 lt1619 gnd + + applicatio s i for atio wu uu
8 lt1619 power mosfet mosfet power dissipation can be separated into fre- quency independent and frequency dependent compo- nents. the r ds(on) loss in the switch is the product of the mean square switch current and switch r ds(on) and it does not vary with the operating frequency. the frequency-dependent switching losses consist of 1) switch transition loss due to finite rise and fall times of the drain source voltage and the drain current 2) gate switch- ing loss, i.e., a packet of charge q g (the total gate charge) which is moved from the gate drive power supply to ground in every switch cycle, and 3) the drain switching loss, charge stored on the parasitic drain capacitance, c oss is dumped to ground as the switch is turned on. the transistor loss can be expressed as: p loss = i drms 2 r ds(on) + transition loss + q g v g f s + 1/2c oss v ds(off) 2 f s where the transition loss can be estimated with: transition loss i cv f i d rss ds off s g avg = () () 2 q g = the total gate charge v g = gate drive voltage ? v drv i g(avg) = the average mosfet buffer output current f s = operating frequency c rss = the average c gd between v ds = 0v and v ds = v ds(off) at low v ds(off) ( 12v) and operating frequencies below 500khz, the ohmic losses often dominate. for high voltage converters, the transition loss and c oss charge dumping loss can dramatically impact the converter efficiency. mosfets with lower parasitic capacitances but higher r ds(on) may actually provide better efficiency in these situations. capacitors in a switch mode dc/dc converter, output ripple voltage is the product of the equivalent series resistance (esr) of the output capacitor and the peak-to-peak capacitor current. depending on topology, current feeding the out- put capacitor can be continuous or discontinuous. the input current can also be continuous or discontinuous even if the inductor current itself is continuous. in boost topology, the inductor is in series with the input source so the input current is continuous and the output current is discontinu- ous. in buck-boost or flyback converters, the inductor is not in series with the input source nor the output, so nei- ther the input current nor output current is continuous. whenever a terminal current is discontinuous, the capaci- tor at that terminal should be chosen to handle the ripple current. capacitor reliability will be adversely affected if the ripple current exceeds the maximum allowable rat- ings. this maximum rating is specified as the rms ripple current. several capacitors may be mounted in parallel to meet the size and ripple current requirements. besides the ripple voltage requirements, the output ca- pacitor also needs to be sized for acceptable output voltage variation under load transients. current sensing resistor r sense the lt1619 drives a low side n-channel mosfet switch. the switch current is sensed with an external resistor r sense connected between the source of the mosfet and ground. the internal blanking circuit blocks the voltage spike developed across r sense for 280ns at switch turn- on. the switch is turned off when the instantaneous voltage across r sense exceeds the current limit threshold, v sense . allowing variations in v sense yields: r v i sense sense min lmax = () () the current limit threshold is constant and does not vary with duty ratio. due to low signal level of the sense voltage, low inductance sense resistors are required to reduce switching noise. low tc resistors maintain constant current limit over temperature. dale wsl and irc series sense resistors meet these criteria. applicatio s i for atio wu uu
9 lt1619 diode schottky diodes are recommended for low output voltage applications because of their low forward voltage. since schottky diodes have negligible stored charge, charge dumping loss is also reduced. the reverse breakdown voltage of the diode should exceed the maximum reverse voltage stress of the topology used. the diode should also be able to carry the peak diode current with acceptable foward voltage. for the boost converter in figure 1, the peak inductor current is approximately 5a. a motorola mbrd835 is used due to its low forward voltage. lowering burst mode operation current limit the lt1619 automatically enters burst mode operation as v c voltage falls below v b . the corresponding switch current is the burst mode operation switch current thresh- old, i d(burst) . the effective burst mode operation current threshold can be lowered by adding an offset to the input of the current sense amplifier so that the switch current appears higher to the pwm comparator. this has the effect of shifting the v c operating range above v b . although burst mode opera- tion is not entirely disabled, the peak switch current before entering burst mode operation is greatly reduced due to the offset of the current sense amplifier. the peak switch current is also determined by the current sense amplifier blanking. to lower the burst mode operation current sense thresh- old, a resistor r os is added between the sense pin and the sense resistor r sense (figure 5). the input bias current i bias of the current sense amplifier, which has a tolerance of 25% and is temperature stable, develops an offset voltage at the sense input. the value of r os required for non-burst mode operation can be obtained with the expression: i bias r os 3 v sense(burst) where v sense(burst) = (burst mode operation peak switch current, i d(burst) ) ? r sense for example, if i bias = 120 m a and v sense(burst) = 10mv: r mv a os 3 m =w 10 120 83 allowing for 25% and 30% variations in i bais and v sense(burst) respectively: r os = (1.25)(1.3)(83 w ) choose r os = 137 w to completely disable burst mode operation. lower values of r os (for example, 50 w to 100 w ) can be used to lower the effective burst mode current limit. the value of the sense resistor is then adjusted to compen- sate for the reduced full-scale sense voltage. i bias r os + i l(max) r sense = 40mv filtering current sense signal i n a current mode converter, the current sense circuit senses the switch current and terminates the switch conduction. in the lt1619, the current sense amplifier has a full-scale input voltage range from the ground to the current limit threshold (53mv). due to high speed switch- ing transients and parasitic trace inductances, the current sense signal v sense tends to be noisy. if the v sense switching transient is excessive, the current sense ampli- fier will amplify the spurious transient instead, resulting in jittery operation. in situations where the internal leading edge blanking is inadequate, a lowpass filter (figure 6) with corner frequency about 5 times the switching fre quency can be used to further attenuate high speed switching transients. in figure 6 the lowpass filter r os and c s has a corner frequency of: figure 5. lowering burst mode operation current limit + 5 4 gnd sense r sense r os current sense amplifier i bias = 120 a 1619 f05 i d i bias = 120 a applicatio s i for atio wu uu
10 lt1619 f rc f corner os s s =? 1 2 5 p (the input impedance of the sense amplifier at the sense pin is 2500 w and r os is typically less than 137 w .) typical values for r os and c s are 100 w and 1nf. the 100 w value for r os reduces burst mode threshold; use 10 w and 10nf when this is not desireable. figure 7. implementing undervoltage lockout + v v i 0 zener diode avalanche diode bv < 5v i figure 8. i-v characteristics of zener and avalanche breakdown diodes s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense lt1619 r3 c1 r4 v in 1619 f09 figure 9. filtering input voltage ripple in uvlo circuit use of shutdown function to modify undervoltage lockout the lt1619 is designed to operate from an input supply with voltage as low as 1.85v. shutdown is activated when the s/s pin is pulled below 0.45v. the shutdown threshold is slightly greater than one junction diode forward voltage and has the temperature characteristics of a junction diode. the s/s pin is normally tied to the input when operating from a low voltage input source. consider the 12v to C 65v isolated flyback converter (see typical applications). the converter draws 3a at low line while delivering 0.4a to the output. if the s/s pin is tied to the input, then the lt1619 will start switching as soon as v in exceeds the internal uvlo threshold. with full load, the converter can draw much higher than the steady-state 3a from the input source during start-up. if the input source is current limited, the input voltage will collapse and latch low. the start-up problem can be prevented by adding a zener diode and a resistor to the s/s pin (figure 7). this is equivalent to increasing undervoltage lockout voltage of the controller. before v in exceeds the zener voltage v z , the s/s pin current is shunted to the ground through the figure 6. current sense filter for improving jitter performance resistor r3. the voltage developed across r3 due to i s/s should be less than the shutdown threshold. the lt1619 remains off until v in exceeds the sum of v z and the shutdown threshold. true zener diodes (bv < 5v) and higher voltage avalanche diodes have different i-v charac- teristics (figure 8). they need to be biased appropriately (value of r3) in order to obtain correct uvlo threshold. when implementing uvlo with converters with high input ripple voltages (such as flyback and forward), the circuit in figure 7 is modified and shown in figure 9. pwm comparator current sense amplifier sense c s r sense v sense + r os i d gnd 1619 f06 lt1619 + 5 4 s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense lt1619 r3 v z v in i s/s 1619 f07 i s/s v s/s = 0 r3 < shutdown threshold ? a uvlo threshold = v z + shutdown threshold v z + v be () i s/s v s/s = 0 applicatio s i for atio wu uu
11 lt1619 here the input voltage ripple is filtered with r3, r4 and c1 so as to prevent the input ripple from falsely tripping the lt1619 synchronization circuit. it is recommended that: rr and rrc f osc 4 1 5 3 1 2341 ? p () << || implementation of hysteretic uvlo with external synchronization the uvlo circuit shown in figure 10 operates down to 0.9v supply voltage. algebraically the uvlo trip points are: s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense lt1619 r9 510k r7 51k v in clk d1 bat85 q2 2n2222 v in upper trip point = 10v v in lower trip point = 8.4v 1619 f10 r8 30k 8.2v r5 51k + r6 51k q1 2n2222 figure 10. addition of hysteresis uvlo while synchronizing the lt1619. component values shown are for the upper and the lower v in trip points of 10v and 8.4v. in uvlo, the gate drive is disabled by pulling the v c pin low. disabling the clock shuts down the lt1619. if not synchronized, the collector of q2 can be tied to the s/s pin and the diode d1 can be eliminated the collector votage of q2 is made about 1.4v at the v in lower trip voltage. this is necessary to prevent the uvlo circuit from interfering with the feedback amplifier in the lt1619. trickle current start from high voltage supplies the low shutdown and idle mode quiescent supply cur- rents of the lt1619 can be utilized to implement trickle current start from high voltage input sources (such as a 36v to 72v telecom bus). the trickle current start-up circuit in figure 11 is modified from the uvlo circuit of figure 10. r10 is a high value resistor that charges the storage capacitor c2 during start-up. before v cc reaches the upper uvlo trip point, q2 holds the s/s pin low. the lt1619 draws shutdown mode current ( ? 15 m a) from v cc . q2 collector can also be tied to the v c pin through a diode as in figure 10. the lt1619 will then draw idle mode quiescent current ( ? 140 m a) from v cc . r10 should be able to charge c2 while supplying current to the uvlo circuit and the lt1619. maximizing r5 to r9 values reduces power dissipation in r10. when v cc crosses the upper uvlo threshold, the lt1619 starts switching and its current consumption increases. before the bootstrap takes over, the lt1619 draws its current from c2. v cc ramps towards the lower uvlo threshold. increasing the value of c2 allows more time for the bootstrap circuit to establish itself before the converter enters undervoltage lockout. s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense lt1619 bootstrap winding t1 d2 r9 r7 v cc hv v in q2 1619 f11 r8 c2 r10 r5 r6 q1 figure 11. trickle current start-up with bootstrapped v cc vvv r rr and v rrr r vv rrr rr r r uvlo hysteresis v v r rrr v v r rr r inh z be inl z be inh inl z be =+ + ? ? ? ? = + () + + () + () ? ? ? ? ? == ++ ? ? ? ? + 1 5 67 579 5 579 56 7 9 5 579 5 67 5 || || || || || || || || r r r 79 6 + () ? ? ? ? ? applicatio s i for atio wu uu
12 lt1619 increasing ramp compensation while synchronizing the lt1619 is synchronized by forced discharge of the internal timing ramp. the timing ramp amplitude de- creases as the synchronization frequency increases. since the internal compensation ramp is derived from the timing ramp, reduced timing ramp results in diminished com- pensating ramp. if the lt1619 is synchronized at frequen- cies 20% to 30% higher than the free-running frequency, external ramp compensation will be required. figures 12 and 13 show two such schemes. in both figures the compensating ramps are kept linear by making r11-c1 and r14-c2 products substantially higher than the synchronizing period. the compensation ramps, whose peak amplitudes are made between 1/4 to 1/3 of the current limit threshold, are developed across r13. as a result, the effective current limit threshold is reduced by the sum of the compensating ramp and the offset voltage developed across r13 due to the sense pin input bias current (see figure 5). moreover, the current limit thresh- old becomes duty cycle dependent. pc board layout and other practical considerations the following is recommended for pc board layout: 1. trace lengths of the branches carrying switched cur- rent should be kept short. for example, in the boost converter of figure 1, the circuit loop formed by m1, r sense , d1 and c out carries switched current. the size of this loop must be minimized. r sense and c out should be grounded to a single point on a large ground plane. this reduces switching noise and overall con- verter jitter. it is also preferable to ground the input capacitor c1 close to the common point between c out and r sense although this is less important. 2. keep the trace between the sense resistor and the sense pin short. when sensing high switch current, kelvin connection to r sense is necessary. 3. bypass both the v in and drv pins with ceramic capaci- tors next to the ic and the ground plane. 4. keep high voltage switching nodes, such as the drain and gate of the mosfet, away from the fb and v c pins. 5. use inductor so that its ripple current is between 1/4 and 1/3 of its peak current. steeper inductor current ramp results in sharper pwm comparator switching, hence less jitter. 6. in most cases, filtering the current sense signal is not necessary for jitter-free operation. figure 14 is the pc board layout for the 5v/8a and 12v/5a boost converters shown in figures 15a and 16a. s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense lt1619 r sense clk d2 1n4148 q1 2n2222 r11 100k r12 2200 r13 51 main power transistor c1 220pf 1619 f12 s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense lt1619 r sense clk d2 1n4148 d3 1n4148 r14 8200 r15 2400 r13 51 c2 2.2nf 1619 f13 figure 12. increasing ramp compensation. q1 buffers the c1 ramp. d2 discharges c1. values shown are for 10v gate drive and 15mv ramp across r13 at 90% duty cycle and 500khz figure 13. externally increasing ramp compensation. similar to figure 12 except that c2 is not buffered with transistor applicatio s i for atio wu uu
13 lt1619 1 2 3 4 8 7 6 5 g g s dd c in2 lt1619 m1 r sense v out v in s m1 c drv 1619 f14 gnd r1 r c c p d1 l1 c z c in1 c out1, 2 r2 figure 14. recommended component placement for the boost converters in figures 15a and 16a applicatio s i for atio wu uu
14 lt1619 applicatio s i for atio wu uu s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense lt1619 + r c 75k c z 15nf c in1 : sanyo poscap 6tpb150m 2 c out1 : sanyo poscap 10tpb220m 4 d1: motorola mbrb1545ct l1: sumida ceph149-1r0 r sense : panasonic 0.002 1w c in2 1 f ceramic c in1 300 f + c out1 220 f 4 l1 1 h v in d1 m1 fds6680a 2 c drv 0.1 f ceramic c p 150pf r sense c out2 10 f ceramic r1 37400 5v 8a 1619 f15a r2 12400 figure 15a. 3.3v to 5v/8a boost converter load current (a) 0.01 83 efficiency (%) 87 88 89 0.1 1 10 1619 f15b 86 85 84 v in = 3.3v figure 15b. efficiency of the 5v/8a boost converter
15 lt1619 applicatio s i for atio wu uu s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense lt1619 + r c 68.1k c z 2200pf c in1 : sanyo os-con 10sa100m c out1 : sanyo os-con 16sa150m 4 d1: motorola mbrb1545ct l1: sumida cdep149-1r8 r sense : panasonic 0.002 1w c in2 1 f ceramic c in1 100 f + c out1 600 f l1 1.8 h v in d1 m1 fds6690a 2 c drv 0.1 f ceramic c p 47pf r sense c out2 10 f ceramic r1 107k 12v 5a 1619 f15a r2 12400 figure 16a. 5v to 12v/5a boost converter load current (a) 0.01 89 efficiency (%) 90 91 92 93 0.1 1 10 1619 f16b 88 87 86 85 94 95 v in = 5v figure 16b. efficiency of the 12v/5a boost converter
16 lt1619 figure 17a. 5v to C 48v cuk converter load current (ma) 10 79 efficiency (%) 81 83 85 87 100 1000 1619 f17b 90 89 80 82 84 86 88 v in = 5.25v v in = 4.75v v in = 5v figure 17b. efficiency of the 5v to C 48v cuk typical applicatio s u 10 f sud45n05-20l 50v, 0.018 43nc 1 f t1 4.7 f film 22nf t1: coiltronics ctx02-14261, efd20-3f3, 6 windings each, 12 h 2.2nf 15 1619 f17a 30 220pf 2n5210 36k 1.1k + 470 f 35v sanyo mv-gx 48v/0.5a + 470 f 35v sanyo mv-gx s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense 4.7 f film mbrs340t3 mbrs340t3 1500 f 6.3v sanyo mv-gx 1n749 4.3v v in 4.75v to 5.25v 2n5210 10.5k 1% 12k 1m 0.007 432k 1% lt1619 +
17 lt1619 figure 18a. isolated local slic power supply (flyback) 20w total output power (65v/0.3a or 32.5v/0.6a) t1 w1 w2 w3 w4 10 f irlr024n 55v, 0.065 q g = 15nc 330pf 50v 1 f 0.1 f 150 f 20v sanyo 20sv150m (os-con) 43 mbrs1100t3 1619 f18a 43 1/4w 100 82k 20k 8.1v 10k s/s fb v c gnd 8 7 6 5 1 2 3 4 v in drv gate sense 1k 1w 1 f 50v 330pf 100v 2.2 f 40v 470pf 2.2 f 40v 32.5v 65v 0.22 f 50v mbrs1100t3 mbrs1100t3 v in 10.5v to 13.7v 0.008 62k 100 6.2v 10k 470 cny17-3 121 lt1431cz 220pf 2.49k t1 philips efd20-3f3-a100-s core set (0.013" gap, ai = 100nh/t 2 w4 6t trifilar 28awg w1 6t trifilar 28awg w3 24t 28awg w2 24t 28awg 2mil polyester film lt1619 load current (ma) 10 50 efficiency (%) 60 70 90 100 1000 1619 f18b 80 55 65 85 75 v in = 13.7v v in = 12v v in = 10.5v figure 18b. efficiency of the isolated local slic (flyback) typical applicatio s u
18 lt1619 dimensions in inches (millimeters) unless otherwise noted. package descriptio n u ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660) msop (ms8) 1098 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" (0.152mm) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.040 0.006 (1.02 0.15) 0.012 (0.30) ref 0.006 0.004 (0.15 0.102) 0.034 0.004 (0.86 0.102) 0.0256 (0.65) bsc 12 3 4 0.193 0.006 (4.90 0.15) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102)
19 lt1619 dimensions in inches (millimeters) unless otherwise noted. package descriptio n u s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 lt1619 1619f lt/tp 1000 4k ? printed in usa ? linear technology corporation 2000 part number description comments lt1370 500khz, 6a switching regulator boost, buck, flyback, forward, inverting; 42v switch voltage lt1372 500khz, 1.5a switching regulator so-8, 2.7v v in 30v, 42v switch voltage lt1613 1.4mhz, sot-23 dc/dc converter fixed frequency, 0.9v v in 10v, 36v switch voltage ltc1624 switching regulator controller so-8, drives n-ch mosfet, 3.5v v in 36v lt1680 synchronous boost controller synchronous operation for high current/high efficiency ltc1872 sot-23 boost controller 550khz fixed frequency, current mode lt1949 600khz, 1a dc/dc converter msop8, 1.5v v in 12v, low-battery detector related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com typical applicatio u v in drv lt1619 gate sense fb s/s 14 r9 2.2k c4, c5: vitramon vj1825y155mxb (1825/x7r) c6: taiyo yuden lmk325bj106mn (1210/x7r) c8: taiyo yuden emk316bj105ml (1206/x7r) t1: coiltronics vp1-0190 (er11/5, 6 windings each 12.2 h) r7 30 d3 mbrs0530t1 q3 mmft3055vl d2 mbrs340t3 q1 fmmt3904 d4 1n4687 4.3v low level (i zt = 50 a) c9 2.2nf c8 1 f 16v c7 220pf 3 876 6 3 5 2 5 2 gnd v c r8 0.015 r10 1.24k 1% r5 100 r6 3.74k 1% c1 0.022 f c6 10 f 10v v out 5v 0.5a 1619 ta01 c5 1.5 f 100v 10 t1 7 11 8 4 1 12 9 c4 1.5 f 100v v in 4v to 28v r3 5.6k figure 19. 2.5w, 4v in -28v in to 5v/0.5a nonisolated supply

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